A. Field of the Invention
The present invention relates to a semiconductor device having a surge voltage protection device protecting the semiconductor device against a surge voltage such as an ESD (Electro-Static-Discharge).
B. Description of the Related Art
In a semiconductor device such as a power IC (integrated circuit), an ESD protection device connected to an input terminal for protecting a surge voltage is generally arranged adjacent to a pad electrode to which wire bonding is performed.
Compared with this, for decreasing a chip area, a semiconductor device is developed which has an ESD protection device arranged beneath a pad electrode. In the following, an example of a related semiconductor device will be explained which has an ESD protection device arranged beneath a pad electrode.
FIG. 8 is a cross sectional view showing the principal part of semiconductor device 500 having a related ESD protection diode. The drawing is a cross sectional view showing the principal part in the vicinity of ESD protection diode 501.
ESD protection diode 501 of semiconductor device 500 includes p-layer 152 arranged on p-type semiconductor substrate 151, LOCOS oxide films 153 arranged on p-layer 152, n-layer 154 arranged between LOCOS oxide films 153 on p-layer 152 and p-layer 155 arranged between the LOCOS oxide films 153 on p-layer 152 in a region different from the region of n-layer 154.
Moreover, ESD protection diode 501 includes insulating film 156 arranged on LOCOS oxide film 153 and on n-layer 154, contact holes 157 arranged in insulating films 156 and LOCOS oxide film 153, and pad electrode 158 arranged on insulating film 156 over n-layer 154 to make electrical contact with n-layer 154 through contact holes 157.
ESD protection diode 501 further includes metal electrode 159 arranged on insulating films 156 to make electrical contact with p-layer 155 in isolation from pad electrode 158, and passivation film 160 arranged on the surface of ESD protection diode 501 with an opening provided on pad electrode 158.
Pad electrode 158 is the cathode electrode of ESD protection diode 501 and metal electrode 159 is an anode electrode. Moreover, metal wiring is connected to the anode electrode (not shown). Furthermore, bonding wire 161 is fixed to pad electrode 158.
FIG. 9 is a diagram showing a relationship between the voltage and the current of related ESD protection diode 501. A solid line is the current to voltage characteristic curve when the size of ESD protection diode 501 is on the order of 0.5 mm×0.5 mm, for example, and a dotted line is the current to voltage characteristic curve when the size is on the order of 80 μm×80 μm, for example. In the diagram, a current rises at the avalanche voltage Vav of ESD protection diode 501. An operating resistance is represented by a reciprocal of the slope (current÷voltage) of the current to voltage characteristic curve which slope depends on a lateral resistance R in the case in which p-layer 152 and p-type semiconductor substrate 151 are combined (for the sake of convenience, in FIG. 8, the lateral resistance is shown in p-type semiconductor substrate 151).
As is shown by the solid line, by increasing the slope, a surge voltage can be effectively clamped. By clamping a surge voltage, the internal circuit (a circuit formed of a device such as a MOSFET) of semiconductor device 500 can be protected from damage due to a surge voltage.
In JP-A-6-163841, a protecting circuit is described which uses a diode, an npn bipolar transistor and a resistance. In JP-A-2005-223026, a description is given with respect to a semiconductor device in which a pad and protection device are integrated with the use of an epitaxial substrate and metal wiring to be bonded and wiring via a diode are connected to an internal circuit. In JP-A-2006-196487, there is described the formation of a protecting transistor beneath a pad. In addition, in each of JP-A-2010-239119 and JP-A-2012-43845, it is described that protecting bipolar transistors to be provided between an input terminal and the ground are formed in parallel. Further in JP-A-2010-239119, it is described that a balancing resistance is connected to each of the protecting bipolar transistors to equalize currents flowing in the protecting bipolar transistors.
In FIG. 8, a decrease in the size of ESD protection diode 501 results in a decrease in the slope of the current to voltage characteristic curve shown by the dotted line in FIG. 9. This means that an operating resistance increases to make it difficult to protect the internal circuit of semiconductor device 500 against a surge voltage.
Moreover, in FIG. 8, holes 165, produced by avalanche which occurred at the pn-junction of n-layer 154 and p-layer 152, reach p-layer 155 (contact layer) to drift toward metal electrode 159 through a region with the lateral resistance R into which region p-layer 152 and p-type semiconductor substrate 151 are combined. Since holes 165 are major carriers in p-layer 152 and p-type semiconductor substrate 151, no decrease in a resistance value due to conductivity modulation is caused. Therefore, the value of the lateral resistance R is just as the resistance value obtained from a diffusion profile of impurities and is large. Thus, the operating resistance of ESD protection diode 501 becomes relatively large. The increase in the area of n-layer 154 for decreasing the operating resistance causes the chip area to increase. The operating resistance is expressed by the reciprocal of the slope of the current to voltage characteristic curve (current/voltage) shown in FIG. 9.
ESD protection diode 501 can be used for a circuit (internal circuit) operated under an operating voltage of 5V, which circuit is fabricated by a process of the process rule of 1 μm. ESD protection diode 501, however, is difficult to apply to an internal circuit fabricated by the process rule of 1 μm or less according to a recent scaled-down IC process. Because the driving voltage of an internal circuit fabricated by the process rule of 1 μm or less is lowered to be lower than 5V.
An ESD protection diode applied to an internal circuit, fabricated by the scaled-down process and having a lowered driving voltage, necessitates a low operating voltage, which requires lowering the reverse breakdown voltage of the ESD protection diode.
For lowering the reverse breakdown voltage of the ESD protection diode, the impurity concentration in a drift layer (p-layer 152) is generally increased. This, however, increases a leak current at a high temperature. Thus, it is difficult to lower the reverse breakdown voltage of the ESD protection diode.
In JP-A-2010-239119, it is described that for simultaneously conducting a plurality of protecting bipolar transistors formed in the semiconductor device, a balancing resistance is provided for each of the protecting bipolar transistors. This, however, increases the occupied area of the ESD protection device to increase the chip area. Moreover, the scattering in the values of the balancing resistances causes currents to concentrate into one protecting bipolar transistor to make the ESD protection device liable to be damaged.
Also in JP-A-2010-239119, a configuration is described in which the protecting bipolar transistors are operated to protect the internal circuit when a high voltage such as an ESD surge is applied. However, no description is presented with respect to the lowered operating voltage of the ESD protection device to cope with the lowered driving voltage of the internal circuit associated with a scaled-down IC process.
Moreover, in each of JP-A-6-163841, JP-A-2005-223026, JP-A-2006-196487, JP-A-2010-239119 and JP-A-2012-43845, there is no description with respect to a configuration of decreasing the impurity concentration in the semiconductor layer, which is to be the base of the parasitic bipolar transistor, to be lower compared with the impurity concentration in the semiconductor layer to be the anode of the parasitic diode. In addition, there is no description with respect to a configuration of decreasing the operating resistance of an ESD protection device by forming the protecting device with a combination of a large number of parasitic npn transistors and a large number of parasitic diodes to make the parasitic npn transistors have snapbacks occur in order and turned-on.
It is an object of the invention to solve the foregoing problems and provide a semiconductor device provided with a protection device with a low operation voltage.